1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and specifically relates to lowering power consumption of a system LSI (Large Scale Integration).
2. Description of Related Art
Technology referred to as dual threshold voltage/power supply voltage (hereinafter described as “dual Vt/Vdd”) exists as a design method for lowering LSI power consumption. This technology is designed in the following manner.
With a semiconductor element forming a critical path, the threshold voltage (Vt) is lowered, and the power supply voltage (Vdd) is raised. On the other hand, with a semiconductor element that does not form a critical path, the threshold voltage (Vt) is raised, and the power supply voltage (Vdd) is lowered.
Power consumption at the time of operation of the LSI, as well as sub-threshold leakage current and sub-threshold leakage current when the system LSI is in standby, are reduced using the aforementioned design technology. A specific example for implementing the above content is disclosed in claim 2 of Japanese patent document 1 (Japanese patent Laid-open publication No. 2001-016592), for example. Further, results of reduced power consumption of 60 to 65% when applying the technology disclosed in non-patent publication 1 (David Kung, et al., “Pushing ASIC Performance in a Power Envelope”, DAC 2003, Jun. 2, 2003) to actual LSI's are disclosed.
However, there are problems with LSI's of the related art where compatibility cannot be achieved when functions divided between a plurality of LSI's are mounted on a single system LSI. For example, when the process technology becomes 90 nm to 65 nm, it is possible to integrate several hundred million transistors (Tr) on a single chip of a system LSI.
To give an example, conventionally, an audio processing function, a photographic image processing function such as, for example, JPEG (Joint Photographic Experts Group) processing, and an image processing function such as, for example, MPEG (Moving Picture Experts Group) 2 processing have been implemented using individual chips. However, it has become possible to implement these functions on a single system LSI.
Further, semiconductor integrated circuits having an SOI (Silicon On Insulator) structure have been developed and market expansion is anticipated. Currently, dual Vt/Vdd technology is effective technology for semiconductor integrated circuits employing normal silicon substrates, and is also technology exhibiting this value for semiconductor integrated circuits having an SOI structure.
However, in the event that dual Vt/Vdd technology is used in semiconductor integrated circuits having an SOI structure, specific problems exist for SOI structure semiconductor integrated circuits that do not exist in semiconductor integrated circuits employing normal silicon substrates.
For example, with SOI structure semiconductor integrated circuits, substrate potential can be set each P-channel semiconductor element and each N-channel semiconductor element. This will bring about various benefits in the future but also conversely raises a new problem of how to set substrate potential of P-channel semiconductor elements and N-channel semiconductor elements while reducing the amount of power supply wiring.